Skip to main content

Overview

The BRIDGE lab focuses on interdisciplinary research to create gateways between Computer Architecture and Physical Design Automation. The phenomenal growth of integration capacity accompanied with growth in design complexity has far outpaced the development in design automation tools and widely adopted design methodologies.

Bridge Overview Figure

The BRIDGE lab investigates novel system design paradigms to build a foundation for holistic system design through design automation. The collaborative research projects span across multiple cross-disciplinary topics including energy efficiency and reliability in multicore systems, high throughput design automation, reliable NOC design and 3D IC design.

Selected Recent Publications

  • TVLSI-17: Prabal Basu, Rajesh JayashankaraShridevi, Koushik Chakraborty and Sanghamitra Roy,"IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms", IEEE Transactions on Very Large Scale Integration Systems, 2017 (Accepted)
  • DATE-17: Aatreyi Bal, Shamik Saha, Sanghamitra Roy, and Koushik Chakraborty, “Revamping Timing Error Resilience to Tackle Choke Points at NTC Systems,”Proceedings of the IEEE/ACM Design Automation and Test in Europe, March 2017, Lausanne, Switzerland (Accepted).
  • TODAES-17:  Shamik Saha, Prabal Basu, Chidhambaranathan R, Aatreyi Bal, Koushik Chakraborty, and Sanghamitra Roy, "SSAGA: SMs Synthesized for Asymmetric GPGPU Applications", ACM Transactions on Design Automation of Electronic Systems (Accepted).
  • ICCAD-16: Chidhambaranathan R, Rajesh JayashankaraShridevi, Sanghamitra Roy, and Koushik Chakraborty, "BoostNoC: Power Efficient Network-on-Chip Architecture for Near Threshold Computing", IEEE/ACM International Conference on Computer-aided Design, November 2016, Austin, Texas.
  • DAC-16: Prabal Basu, Hu Chen, Shamik Saha, Koushik Chakraborty, and Sanghamitra Roy, "SwiftGPU: Fostering Energy Efficiency in a Near-Threshold GPU Through Tactical Performance Boost", Proceedings of the 53rd IEEE/ACM Design Automation Conference, June  2016, Austin, Texas.
  • DAC-16: Rajesh JayashankaraShridevi, Chidhambaranathan R,Sanghamitra Roy, and Koushik Chakraborty, "Catching the Flu: Emerging threats from a Third Party Power Management Unit", Proceedings of the 53rd IEEE/ACM Design Automation Conference, June  2016, Austin, Texas. accepted for publication.
  • DAC-16: Atif Yasin, Jeff Zhun, Siddharth Garg, Hu Chen, Sanghamitra Roy, and Koushik Chakraborty, "Synergistic Timing Speculation for Multi-threaded Programs", Proceedings of the 53rd IEEE/ACM Design Automation Conference, June  2016, Austin, Texas, accepted for publication.
  • DATE-16: Prabal Basu, Rajesh JayashankaraShridevi, Koushik Chakraborty and Sanghamitra Roy, "PRADA: Combating Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms", Proceedings of the IEEE/ACM Design Automation and Test in Europe, March 2016, Dresden, Germany (Accepted for publication).
  • ISLPED-15: Rajesh JayashankaraShridevi, Dean Michael Ancajas, Koushik Chakraborty and Sanghamitra Roy, "Tackling Voltage Emergencies in NoC Through Timing Error Resilience", Proceedings of the IEEE International Symposium on Low Power Electronics and Design, July  2015, Rome, Italy, accepted for publication (Acceptance Rate 18.2%).
  • DAC-15: Hu Chen, Dieudonne Manzi, Sanghamitra Roy and Koushik Chakraborty, "Opportunistic Turbo Execution in NTC: Exploiting the Paradigm Shift in Performance Bottlenecks", Proceedings of the 52nd IEEE/ACM Design Automation Conference, June  2015, San Francisco, CA, accepted for publication.
  • CODES+ISSS-14: Dean Michael Ancajas, Koushik Chakraborty and Sanghamitra Roy, "Tackling QoS-induced Aging in Exascale Systems through Agile Path Selection", IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (Nomination for Best Paper Award).
  • Robust L1 Cache Design.", IEEE/ACM International Symposium on Quality Electronic Design (Accepted).
  • DAC-14: Dean Michael Ancajas, Koushik Chakraborty and Sanghamitra Roy, "Fort-NoCs: Mitigating the Threat of a Compromised-NoC", IEEE/ACM 51st Design Automation Conference (Accepted).
  • DATE-14Hu Chen, Sanghamitra Roy, and Koushik Chakraborty, "DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors", IEEE/ACM Design Automation and Test in Europe. March 2014. Dresden, Germany.
  • DAC-13: Koushik Chakraborty, Brennan Cozzens, Sanghamitra Roy, and Dean Michael Ancajas, "Efficiently Tolerating Timing Violations in Pipelined Microprocessors", IEEE/ACM 50th Design Automation Conference (Accepted). June 2013, Austin, Texas
  • DAC-13: Dean Michael Ancajas, James McCabe Nickerson, Koushik Chakraborty, and Sanghamitra Roy, "HCI Tolerant NoC Router Micro-architecture", IEEE/ACM 50th Design Automation Conference (Accepted). June 2013, Austin, Texas
  • DAC-13: Dean Michael Ancajas, Koushik Chakraborty, and Sanghamitra Roy, "DMR3D: Dynamic Memory Relocation in 3D Multicore Systems", IEEE/ACM 50th Design Automation Conference (Accepted). June 2013, Austin, Texas
  • DATE-13Dean Michael Ancajas, Koushik Chakraborty, and Sanghamitra Roy, "Proactive Aging Management in Heterogeneous NoCs through a Criticality-Driven Routing Approach", IEEE/ACM Design Automation and Test in Europe (Accepted)

 

 

news header
Congratulations to Prabal and Rajesh for their paper "IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms" accepted for publication in TVLSI 2017.
Congratulations to Aatreyi and Shamik for their paper "Revamping Timing Error Resilience to Tackle Choke Points at NTC Systems" accepted for publication in DATE 2017.
Congratulations to Shamik, Prabal, Chidham and Aatreyi for their paper "SSAGA: SMs Synthesized for Asymmetric GPGPU Applications" accepted for publication in TODAES 2017 journal.
Dr. Sanghamitra Roy has been named among the most influential alumni to graduate from the University of Wisconsin-Madison in recognition of her ongoing success in academia and research. Links to the news release and her interview.

Congratulations!!!
Congratulations to Chidam and Rajesh for their paper "BoostNoC: Power Efficient Network-on-Chip Architecture for Near Threshold Computing" accepted for publication in ICCAD 2016.
Congratulations to Prabal, Hu, Shamik, Rajesh, Chidham, Atif, Jeff, and Siddharth for having all three of their papers accepted for publication in DAC 2016.
Congratulations to Hu and Manzi for their paper "Opportunistic Turbo Execution in NTC: Exploiting the Paradigm Shift in Performance Bottlenecks" accepted for publication in DAC 2015.
Dr. Chakraborty and Dr. Roy receive 2 NSF grants: NSF SATC Award and NSF CNS Core Program Award.

Congratulations!!!
Dean's paper on "Tackling QoS-induced Aging in Exascale Systems through Agile Path Selection" receives nomination for Best Paper Award at CODES+ISSS 2014. Congratulations!!!
Congratulations to Dean Ancajas for his paper on Security on Compromised-NoCs on DAC 2014! DAC 2014 will be held in San Francisco, California. 
Congratulations to Chen Hu for his paper on Dynamically Adaptable Resilient Pipeline Design on DATE 2014! DATE 2014 will be held in Dresden, Germany. 
Two papers from the group are accepted at the 31st International Conference on Computer Design. Jason's paper on Dark Silicon and Yiding's GPU Global Router paper will be presented at the said conference.
Dr. Sanghamitra Roy receives the prestigious NSF CAREER Award (5 year grant). The NSF CAREER Award is given to junior faculties who exemplify the role of teacher-scholars through outstanding research, excellent education and the integration of education and research within the context of the mission of their organizations.
Three papers from the research group have been accepted for publication at the 50th Design Automation Conference
Saurabh and Dean's paper on NBTI Mitigation won the Best Paper Award at ICCD 2012
Two papers from the research group have been accepted at DAC 2012. Kshitij's paper on aging-aware routing algorithm for NOCs and Dr Roy and Dr Chakraborty's paper on prediction of timing violations. Congratulations! See publication page for more info.
Kshitij's Paper on NOC scheduling has been accepted in DATE. He will present it on Germany this coming March 2012.

Congratulations Kshitij!
Satyajit's paper on DRAM process variation has been accepted in ISQED 2012.

Congratulations Satya!
Dr. Chakraborty and Dr. Roy win 3-year NSF Grant from CISE Core Program! Read about it here. 

Congratulations!!!
GPU Global Router paper by Yiding and Dean is accepted at ICCAD 2011 at San Jose, California. 

Congratulations!!!
Dr Chakraborty and Dr Roy's paper on Threshold Voltage assignment for 3D Multicore systems has been accepted at IEEE Transactions on Very Large Scale Integration Systems. Congratulations!!!
Yiding and Vilasita's journal paper about GPU-Floorplanning algorithm has been accepted at ACM TODAES. Congratulations!
Dr Chakraborty and Dr Roy's paper on THPH has been nominated for Best Paper Award at DATE 2011. Their paper is among the Top 5 papers out of 789 submissions (0.63%).
Dr Roy's research on DRAM process variation receives grant from Micron Inc, Boise, Idaho. Congratulations!!
Dr Roy and Dr Chakraborty's wins USTAR Technology Grant to commercialize their project.
Dr Roy and Dr Chakraborty's paper on threshold voltage assignment for 3D Multicore systems wins Best Paper Award nomination.